module mips_tb();
    
   reg clk, rst;
    
   mips U_MIPS(
      .clk(clk), .rst(rst)
   );
   reg[4:0] n;
   initial begin
      $readmemh( "G:/vivado/MultiCycleCPU/MultiCycleCPU.srcs/test/code4.txt" , U_MIPS.U_IM.imem ) ;
      //ALU类型MultiCycleCPU
       $monitor($time,,"state=%s PC=0x%8X Instr=0x%8X PCWr=%d IRWr=%d RFWr=%d DMWr=%d ExtOp=%b ExtOut=%d ALUOut=%d WDSel=%d RegWD=%d\nRegSel=%d WR=%d", 
          (U_MIPS.U_CTRL.state == 0) ? "sif" : 
          (U_MIPS.U_CTRL.state == 1) ? "sid" :
          (U_MIPS.U_CTRL.state == 2) ? "exe3" :
          (U_MIPS.U_CTRL.state == 3) ? "smem" :
          (U_MIPS.U_CTRL.state == 4) ? "wb2" :
          (U_MIPS.U_CTRL.state == 5) ? "exe2" :
          (U_MIPS.U_CTRL.state == 6) ? "exe1" :
          "wb1",
          U_MIPS.U_PC.PC, U_MIPS.Instr, U_MIPS.PCWr,U_MIPS.IRWr,U_MIPS.RFWr,U_MIPS.DMWr,
          U_MIPS.ExtOp,U_MIPS.Imm32,U_MIPS.ALUOut,U_MIPS.WDSel,U_MIPS.RegWD,U_MIPS.RegSel,U_MIPS.WR); 
      
      //DM lw sw
//       $monitor($time,,"state=%b PC=0x%8X Instr=0x%8x PCWr=%d IRWr=%d RFWr=%d DMWr=%d ExtOp=%d ExtOut=%d BSel=%d A=%H B=%H ALUOut=%d DAddr=%H DMWD=%H",
//          U_MIPS.U_CTRL.state,U_MIPS.U_PC.PC,U_MIPS.Instr,U_MIPS.PCWr,U_MIPS.IRWr,U_MIPS.RFWr,U_MIPS.DMWr,U_MIPS.ExtOp,U_MIPS.Imm32,U_MIPS.BSel,U_MIPS.RD1,U_MIPS.ALU_B,U_MIPS.ALUOut,
//          U_MIPS.DAddr,U_MIPS.DMWD);

      // BEQ BNE MDU
//      $monitor($time,,"state=%b PC=0x%8X PCWr=%d IRWr=%d RFWr=%d DMWr=%d RD1=%H RD2=%H Zeor=%d NpcOp=%d",
//         U_MIPS.U_CTRL.state,U_MIPS.U_PC.PC,U_MIPS.PCWr,U_MIPS.IRWr,U_MIPS.RFWr,U_MIPS.DMWr,U_MIPS.RD1,U_MIPS.RD2,U_MIPS.Zero,
//         U_MIPS.NpcOp);

       for(n=0;n<=7;n=n+1)
         $display("%h",U_MIPS.U_IM.imem[n]);
      clk = 1 ;
      rst = 0 ;
      #5
      rst = 1;
      #20 ;
      rst = 0 ;
   end
   
   always
	   #(50) clk = ~clk;
   
endmodule
//G:/vivado/back/MultiCycleCPU
//C:/Users/Administrator/Desktop/MultiCycleCPU/MultiCycleCPU.srcs/test.txt
//File test.txt referenced on C:/Users/Administrator/Desktop/MultiCycleCPU/MultiCycleCPU.srcs/mips_tb.v at line 10 cannot be opened for reading. Please ensure that this file is available in the current working directory.